1. Field of the Invention
The present invention relates to a fractional-N synthesizer, more particularly to a fractional-N synthesizer comprising a loop filer and a charge pump that provides a current to the loop filter.
The present invention further relates to an apparatus comprising a fractional-N synthesizer. Such an apparatus can be a radio frequency communication device, or any other device that needs a fractional-N synthesizer.
2. Description of the Related Art
In Philips(trademark) datasheet SA8028, xe2x80x9c2.5 GHz sigma delta fractional-N synthesizer and 750 MHz auxiliary synthesizerxe2x80x9d, a sigma delta fractional-N synthesizer is disclosed. The SA8028 device integrates programmable dividers, charge pumps and phase comparators to implement phase-locked loops. The synthesizer operates at VCO input frequencies up to 2.5 GHz and has fully programmable main auxiliary, and reference dividers. The main divider is a fractional-N divider with programmable integer ratios from 33 to 509 and uses a second order sigma-delta modulator to achieve a fractional division resolution of 22 programmable bits. The charge pump current is set by an external resistor. Two main charge pumps are driven by a main phase detector, and an auxiliary charge pump is driven by an auxiliary phase detector. Lock detection is available only for the auxiliary phase detector. The SA8028 fractional-N synthesizer operates in two modes operation, a speed up mode for faster switching when the VCO frequency needs to change from one frequency to another, and a normal mode for a better phase noise after locking of the phase-locked loop. In the SA8028 synthesizer, in the speed up mode a loop filter bandwidth is wider than in the normal mode. This is achieved by applying a higher charge pump current to the loop filter at the speed up mode than in the normal mode, a wider bandwidth achieving a faster switching or acquisition time and faster locking, and a narrower bandwidth better suppressing in-band phase noise. In addition to using a higher charge pump current for bandwidth widening, also other parameters of the loop filter may be changed such as reducing resistive elements that determine a main time constant of the loop filter.
It is an object of the invention to provide a fractional-N synthesizer with a substantially increased switching time.
It is another object of the invention to provide such a fractional-N synthesizer of the sigma delta type.
It is still another object of the invention to provide such a fractional-N synthesizer that automatically switches from a speed up mode of operation to a normal mode of operation.
It is still another object of the invention to provide such a fractional-N synthesizer with lock detection, without the need of an auxiliary phase detector.
In accordance with the invention, a fractional-N frequency synthesizer is provided, said fractional-N synthesizer comprising:
voltage controlled oscillator means for providing a frequency output signal;
fractional-N frequency division means for dividing said frequency output signal;
phase comparator means for comparing a reference clock signal with said fractional-N divided frequency output signal;
loop filtering means for filtering a current, said loop filtering means providing a filtered current to said voltage controlled oscillator means, and comprising a capacitive element for receiving said current;
charge pump means for providing said current, said charge pump means being controllable by said phase comparator means, and successively being operable in a first operating mode in which said current has a first value, a second operating mode in which said current has a second value, and a third operating mode in which said current has a third value, said first value being substantially higher than said second and third values, in said first operating mode said charge pump at least substantially being decoupled from said phase comparator means, and in said second and third operating modes said charge pump being coupled to said phase comparator means.
The invention is based on the insight of first operating the synthesizer in open loop mode to maximally explore the charge pump where loop stability is not a determining factor, upon powering up or upon a frequency change, and then operating the synthesizer in closed loop mode for locking and tracking where loop stability is a determining factor. This is because in closed loop mode loop filter bandwidth cannot be increased indefinitely for stability reasons. The invention is further based upon the insight that particularly in sigma delta type fractional-N synthesizers, or the like, where N, the ratio of a desired VCO output frequency and a reference frequency, is substantially smaller than in conventional synthesizers and herewith a capacitor that determines a main time constant in the loop filter is substantially larger. The invention provides pre-charging of such a much larger capacitor, in an open loop mode of operation where loop stability is not a determining factor. The invention is thus based upon the insight that pre-charging is needed, and the further insight that pre-charging time may become a dominant factor in the switching time that is otherwise determined by PLL acquisition time. Because pre-charging is done with an open loop the charge pump can have maximum duty cycle thereby providing a huge charge pump current that very quickly pre-charges the dominant capacitor in the loop filter.
In an embodiment, the three operating modes are implemented using three different current sources as the charge pump means.
In another embodiment, the three operating modes are implemented using two current sources, one current source being operated at pre-charging while being disconnected from the phase comparator, and being operated at speed up while being connected to the phase comparator, i.e., first operating in an open loop and then operating in a closed loop, and another current source being operated in closed loop normal mode.
Preferably, mode switching from speed up mode to normal mode is done automatically, upon locking of the PLL, by using an averaged phase error over a given time window that can be much smaller than the acquisition time. In an embodiment such mode switching is achieved by a low pass filter that is coupled between the phase detector and a switch that switches controlled by the low pass filter, the switch switching off the speed up current upon the PLL entering its locked condition. In an embodiment, a one bit quantizer with a dead zone is used to detect the averaged phase error. If a voltage across a capacitor in the low pass filter is within the dead zone, at a sampling time, a phase lock condition exists and the switch is controlled the synthesizer from speed up to normal mode. In an embodiment, the low pass filter has a switch bridging the capacitor, the switch being closed at given intervals to discharge the capacitor. This is to prevent slow discharge after a locking condition has been detected. In an embodiment, the switch is closed at a given multiple of cycles of the reference clock.
Alternatively, phase error averaging can be achieved by a digital low pass filter where the phase error is sampled and averaged.